Large caches

[ISCA 2011][PDF]
Jayesh Gaur, Mainak Chaudhuri, and Sreenivas Subramoney. Bypass and Insertion Algorithms for Exclusive Last-level Caches. In Proceedings of the 38th IEEE/ACM International Symposium on Computer Architecture, pages 81-92, June 2011.

[MICRO 2009][PDF][Extended results][peLIFO simulation code][peLIFOLite simulation code]
Mainak Chaudhuri. Pseudo-LIFO: The Foundation of a New Family of Replacement Policies for Last-level Caches. In Proceedings of the 42nd IEEE/ACM International Symposium on Microarchitecture, pages 401-412, December 2009.

[HPCA 2009][PDF][Note]
Mainak Chaudhuri. PageNUCA: Selected Policies for Page-grain Locality Management in Large Shared Chip-multiprocessor Caches. In Proceedings of the 15th IEEE International Symposium on High-Performance Computer Architecture, pages 227-238, February 2009.

[MICRO 2007][PDF]
Arkaprava Basu, Nevin Kırman, Meyrem Kırman, Mainak Chaudhuri, and José F. Martínez. Scavenger: A New Last Level Cache Architecture with Global Block Priority. In Proceedings of the 40th IEEE/ACM International Symposium on Microarchitecture, pages 421-432, December 2007.

[ICCD 2007][PDF]
Jugash Chandarlapati and Mainak Chaudhuri. LEMap: Controlling Leakage in Large Chip-multiprocessor Caches via Profile-guided Virtual Address Translation. In Proceedings of the 25th IEEE International Conference on Computer Design, pages 423-430, October 2007.

Parallel programming/Run-time supports

[PACT 2010 poster][PDF]
Santhosh S. Ananthramu, Deepak Majeti, Sanjeev K. Aggarwal, and Mainak Chaudhuri. Improving Speculative Loop Parallelization via Selective Squash and Speculation Reuse. In Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, pages 543-544, September 2010.

[HPC ASIA 2009][PDF]
Pramod K. Bhatotia, Sanjeev K. Aggarwal, and Mainak Chaudhuri. A Compilation Framework for Irregular Memory Accesses on the Cell Broadband Engine. In Proceedings of the 10th Asia Pacific High-Performance Computing Conference, pages 62-69, March 2009.

[SciProg 2009][PDF]
Vishwas B. C., Abhishek Gadia, and Mainak Chaudhuri. Implementing a Parallel Matrix Factorization Library on the Cell Broadband Engine. In Scientific Programming special issue on high-performance computing with Cell BE, 17(1-2): 3-29, February 2009.

Microprocessor architecture

[HPCA 2005][PDF]
[Winner of the best paper award]
Nevin Kırman, Meyrem Kırman, Mainak Chaudhuri, and José F. Martínez. Checkpointed Early Load Retirement. In Proceedings of the 11th IEEE International Symposium on High-Performance Computer Architecture, pages 16-27, February 2005.

Directory controller microarchitecture

[IEEE TPDS 2007][PDF]
Mainak Chaudhuri and Mark Heinrich. Integrated Memory Controllers with Parallel Coherence Streams. In IEEE Transactions on Parallel and Distributed Systems, 18(8): 1159-1173, August 2007.

[ISCA 2004][PDF]
Mainak Chaudhuri and Mark Heinrich. SMTp: An Architecture for Next-generation Scalable Multi-threading. In Proceedings of the 31st IEEE/ACM Annual International Symposium on Computer Architecture, pages 124-135, June 2004.

[IEEE TC 2003][PDF]
Mainak Chaudhuri, Mark Heinrich, Chris Holt, Jaswinder Pal Singh, Edward Rothberg, and John Hennessy. Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation. In IEEE Transactions on Computers, 52(7): 862-880, July 2003.

Directory protocol optimization

[IEEE TPDS 2004][PDF]
Mainak Chaudhuri and Mark Heinrich. Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols. In IEEE Transactions on Parallel and Distributed Systems, 15(8): 699-712, August 2004.

[IEEE TPDS 2004][PDF]
Mainak Chaudhuri and Mark Heinrich. The Impact of Negative Acknowledgments in Shared Memory Scientific Applications. In IEEE Transactions on Parallel and Distributed Systems, 15(2): 134-150, February 2004.

Intelligent memory controller

[ICPP 2007][PDF]
Lakshmana R. Vittanala and Mainak Chaudhuri. Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors. In the 36th IEEE International Conference on Parallel Processing, September 2007.

[ISPASS 2007][PDF]
Dhiraj D. Kalamkar, Mainak Chaudhuri, and Mark Heinrich. Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, pages 242-253, April 2007.

[IEEE TC 2004][PDF]
Daehyun Kim, Mainak Chaudhuri, Mark Heinrich, and Evan Speight. Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems. In IEEE Transactions on Computers, 53(3): 288-307, March 2004.

[IPDPS 2003][PDF]
Daehyun Kim, Mainak Chaudhuri, and Mark Heinrich. Active Memory Techniques for ccNUMA Multiprocessors. In Proceedings of the 2003 IEEE International Parallel and Distributed Processing Symposium, April 2003. (Abstract on page 10)

[PDPTA 2002][PDF]
Mainak Chaudhuri, Daehyun Kim, and Mark Heinrich. Cache Coherence Protocol Design for Active Memory Systems. In Proceedings of the 2002 International Conference on Parallel and Distributed Processing Techniques and Applications, pages 83-89, June 2002.

[ICS 2002][PDF]
Daehyun Kim, Mainak Chaudhuri, and Mark Heinrich. Leveraging Cache Coherence in Active Memory Systems. In Proceedings of the 16th ACM International Conference on Supercomputing, pages 2-13, June 2002.

[ISHPC 2002][PDF]
Mark Heinrich, Evan Speight, and Mainak Chaudhuri. Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters. In Proceedings of the 4th International Symposium on High Performance Computing (Lecture Notes in Computer Science, vol. 2327, pages 78-92, Springer Verlag), May 2002.

Potpourri

[ACM SIGARCH CAN 2006][PDF]
Abhas Kumar, Nisheet Jain, and Mainak Chaudhuri. Long-Latency Branches: How Much Do They Matter? In ACM SIGARCH Computer Architecture News, 34(3):9-15, June 2006. [Errata in PDF]

[ACM SIGARCH CAN 2003][PDF]
Mark Heinrich and Mainak Chaudhuri. Ocean Warning: Avoid Drowning. In ACM SIGARCH Computer Architecture News, 31(3):30-32, June 2003.