Workshop on Architectures and Compilers for Multithreading

December 13-15, 2007
Indian Institute of Technology, Kanpur
Program (Venue: CS101, Department of Computer Science and Engineering)



Prolog

Increasing integration and ever-shrinking process technology have enabled billion-transistor chips. However, the amount of parallelism achievable from a single thread of execution remains limited by the off-chip data access latency. Using this large number of transistors for implementing complex algorithms to hide this latency only buys diminishing return in terms of performance while significantly raising the power bill and verification cost. Chip-multiprocessors offer an energy-efficient way to think about this problem. Devoting the transistors to build a larger number of simple cores can improve performance while keeping the power consumption within projected budget. However, to take full advantage of such a design the programs need to be multithreaded. As chip-multiprocessors crowd the computer market, there is an increasing need for multithreaded software. Today, these applications come from diverse fields such as engineering simulations, web services, financial applications, data center requirements, drug design, weather prediction, genetics, search engines, medical applications like tomography, etc. An application programmer faces a daunting task of parallelizing these applications and must have reasonable knowledge of architecture, compilers, parallel libraries and multithreading. Although parallelizing compilers have come a long way to improve the performance of numerical scientific applications, it is time to extend and refine the existing ideas and explore new ideas so that general integer programs, which dominate the day-to-day desktop workloads, can be parallelized well. It is believed that the compiler designers or the architects alone cannot achieve this holy grail. A collaborative effort is needed to squeeze the last drop of performance out of the future computing platforms. The goal of this workshop is to invite the researchers engaged in contributing to these cross-cutting issues of multithreaded architectures and multithreading compilers and discuss the recent advances in these areas. The workshop will focus on compiler techniques to improve multithreading capabilities and architectural/compiler techniques to improve the programmability, performance, reliability, and fault-tolerance of chip-multiprocessor based systems. The topics of interest include, but are not limited to, the following.

  • Multi-core and many-core architectures
  • On-chip memory hierarchy design for multi-core processors
  • Compiler optimizations for multi-core processors
  • Analysis of multi-threaded programs
  • Parallelizing compilers
  • Run-time supports for parallelization
  • Source pattern-based parallelization
  • Speculative parallelization
  • Transactional memory models
  • Energy-efficient multi-threading
  • Data race and coherence/consistency fault checkers
  • On-chip interconnects
  • Large-scale parallelization (shared memory and message passing)


  • Invited speakers

    Sarita Adve, UIUC (Abstract, Slides)
    Frances Allen, IBM (Abstract, Slides)
    Saman Amarasinghe, MIT (Abstract, Slides)
    Nancy Amato, Texas A & M (Abstract, Slides)
    Arvind, MIT (Abstract, Slides)
    Chen Ding, Rochester (Abstract, Slides)
    Rudolf Eigenmann, Purdue (Abstract, Slides)
    Manish Gupta, IBM (Abstract)
    Maurice Herlihy, Brown (Abstract)
    Laxmikant Kale, UIUC (Abstract, Slides, Charisma addendum)
    Uday Khedker, IIT Mumbai (Abstract, Slides)
    José Martínez, Cornell (Abstract, Slides)
    Mayur Naik, Stanford (Abstract, Slides)
    Ramesh Peri, Intel (Abstract, Slides)
    Keshav Pingali, UT Austin (Abstract, Slides)
    Lawrence Rauchwerger, Texas A & M (Abstract, Slides)
    Vivek Sarkar, Rice (Abstract, Slides)
    Y. N. Srikant, IISc, Bangalore (Abstract, Slides)
    Josep Torrellas, UIUC (Abstract, Slides)
    David Wood, Wisconsin (Abstract, Slides)

    Workshop technical program

    Sessions

    Workshop cultural program

    Excursion to Taj and historic places in the vicinity

    Organizing committee

    Sanjeev Aggarwal, IIT Kanpur
    Arvind, MIT
    Mainak Chaudhuri, IIT Kanpur
    Manish Gupta, IBM
    Keshav Pingali, UT Austin

    Reaching IIT Kanpur

    Dreamz Travel (official travel agents for the workshop)