Abhinav Agarwal
Massachusetts Institute of Technology
Date: Wednesday, January 16th, 2013
Time: 3 PM
Venue: CS102.
One of the more exciting recent developments in DSP algorithms is the newly proposed sub-linear algorithm for computing the DFT of large but sparse signals by Professors Indyk and Katabi and their students at MIT. This algorithm can potentially revolutionize embedded real-time DSP applications working on very large datasets. In this talk, we describe our efforts, in collaboration with the algorithm authors, to build a high-throughput hardware implementation of this Sparse FFT algorithm targeted for FPGAs. This implementation targets processing a new million point input every millisecond, generating the location and values of the top 500 frequencies in the sparse input, while having a power constraint of 1-2 W. The talk will provide a brief description of the algorithm, implementation challenges and our micro-architectural solutions, and the targeted usage of this implementation in wireless applications. Prior knowledge of FFT implementations is not required to follow the talk.
Abhinav Agarwal received his B.Tech in Electrical Engineering from IIT Kanpur in 2006 and M.S. in EECS from MIT in 2009. He is currently a PhD candidate at MIT, where he is a part of the Computation Structures Group, working with Prof. Arvind. His research interests include the automatic power gating of ASIC designs using high-level synthesis and the rapid prototyping of wireless IPs for FPGA and ASIC synthesis.