The course is primarily intended to familiarize students with the problem of testing large and complex electronic circuits.
Various techniques to solve this problem and concepts of design for easy testability (DFT) will be discussed. Topics related to fault-modeling and fault-simulation to evaluate the fault-coverage of test vectors will be covered in detail.
The problem of reduced yield and reliability of circuits in presence of faults will be discussed and techniques to improve the yield and reliability of these circuits by introducing fault-tolerance measures will also be covered.
Various redundancy techniques like structural, time, information and software redundancy will also be discussed in detail.
D. K. Pradhan (Editor).Fault-Tolerant Computing: Theory and Techniques, Prentice Hall, NJ, 1986.
Barry Johnson.Design and Analysis of Fault-Tolerant Digital Systems, Addison Wesley, 1989.
A. Miczo.Digital Logic Testing and Simulation, John Wiley & Sons, 1987.
IEEE Transactions on Computers IEEE Transactions on Computer Aided Design IEEE Transactions on Reliability IEEE Transactions on Solid State Circuits