Seminar by Dr Raghuram Tupuri
Power Aware High Performance Microprocessor Design Challenges
Dr Raghuram Tupuri
Microprocessor Design Group, AMD
Date: Fri, Feb 17, 2006
Time: 1530
Venue: CS 101 Abstract:
With the increasingly large number of transistors on modern day microprocessors, transistor real estate is becoming cheaper and feature sets are growing larger. The ability to increase the performance of these machines is becoming almost independent of the underlying instruction set architecture and the focus is increasingly in the core and memory architecture and their power aware implementations in deep sub micron technologies. In this presentation, we will discuss the instruction set consolidation and the challenges in implementing these complex designs in sub 65nm processor technologies.
About the Speaker:
Dr. Raghuram Tupuri is the General Manager for the Microprocessor design group in AMD, Bangalore and is responsible for the microprocessor design team involved in designing next generation server product. He joined AMD, Austin in 1992 and since then he has been working on X86 microprocessor designs, in particular on micro-architecture, logic/circuit design and design methodologies. Before joining in AMD, Raghuram worked at Texas Instruments for three years. Raghuram also holds an adjunct faculty position in the Computer Engineering department at UT-Austin. His research interests include topics related to power aware highperformance microprocessor design. Raghuram received B.Tech. from Nagarjuna University, M.Tech. from IIT-Kanpur and Ph.D. from the University of Texas at Austin.