Seminar by Prof. Dilip Banerji
A Fast Heuristic for FPGA Placement
Prof. Dilip Banerji
Department of Computing and Information Science
University of Guelph
Guelph, Ontario, Canada
Date: Wednesday, March 17, 2004
Time: 3:45 PM
Venue: CS-101
Abstract
Field-Programmable Gate Arrays (FPGAs) are semiconductor chips that implement digital circuits by configuring programmable logic and their interconnections. The use of FPGAs has grown almost exponentially because they dramatically reduce design turn-around time and start-up costs for electronic products, compared with Application-Specific Integrated Circuits (ASICs). A set of CAD tools is required to compile a hardware description into bitstream files that are used to configure a target FPGA to implement the desired circuit. Currently, the compile time, which is dominated by placement and routing times, can easily take hours or days to complete for large (8 million gate) FPGAs. With 40 million gate FPGAs on the horizon, these prohibitively long compile times may nullify the time-to -market advantage of FPGAs. This talk presents two novel placement heuristics that significantly reduce the amount of time required to achieve high quality placements, compared with a state-of-the-art tool, VPR. The first algorithm is an enhancement of simulated annealing that converges very fast. The second algorithm is based on clustering to reduce the complexity of solution space, followed by de-clustering during which the placement is fine-tuned to produce high quality solutions.
About the Speaker
B.Tech (EE), 1965, IIT, Kanpur
M.Sc (EE), 1967, University of Ottawa, Ottawa, Canada
PhD (Comp Sc), 1970, Univ of Waterloo
Work: Bell Northern Research, Toronto 1970-72
Adjunct Assistant Prof (1970-72), York Univ and Univ of Toronto.
1972-78: Comp Sc Dept, Univ of Ottawa
1978-83: Professor & Dean, School of Computer & Systems Sciences, JNU, New Delhi
1983-to date: Professor, Computing & Info Science, Univ of Guelph, Guelph, Ontario. Also, founding memebr of Modeling & Design Automation Group at Guelph.
Current interests: Design automation for digital systems (behavioral level synthesis, CAD for FPGAs).