Course Contents
The course comprises of four main modules apart from a module on preliminaries.
Module 0: Preliminaries on Processor, Cache, and Memory
Module 1: Shared on-chip Cache Management
(i) Cache management policies (insertion, eviction, promotion, and bypassing)
(ii) Multi-core cache hierarchies (inclusive, exclusive, and non-inclusive) and static/dynamic non-uniform caches
(iii) Latency tolerance techniques (hardware prefetching and cache compression)
Module 2: DRAM Systems
(i) DRAM controllers, timing constraints, DRAM organization, DRAM modeling issues
(ii) DRAM scheduling policies and DRAM address mapping schemes
(iii) Management of DRAM capacity, bandwidth, energy, and power
Module 3: Secure/reliable Memory
(i) Side/covert-channel attacks, cold boot attacks at the cache and DRAM
(ii) DRAM scaling challenges, reliability issues, and row-hammer problem
Module 4: Emerging Topics
(i) 3D/2.5D DRAM stacking, DRAM cache, PCM, 3D X-point, and processing-in-memory
(ii) Memory hierarchy for approximate computing and memory for large-scale systems