Translation-Triggered Prefetching, Abhishek Bhattacharjee, ASPLOS 17 (Will be presented by Biswa) <br/>

Efficient Address Translation for Architectures with Multiple Page Sizes, Guilherme Cox; Abhishek Bhattacharjee, ASPLOS 17  <br/>

Do-It-Yourself Virtual Memory Translation, ISCA 17  <br/>

Hybrid TLB Coalescing: Improving TLB Translation Coverage under Diverse Fragmented Memory Allocations, ISCA 17  <br/>

Agile Paging: Exceeding the Best of Nested and Shadow Paging, ISCA 16  (Will be presented by Deba) <br/> 

RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization, MICRO 13  <br/>

Large-reach memory management unit caches, MICRO 13  <br/>
                         
Towards Practical Default-On Multi-Core Record/Replay, ASPLOS 17  <br/>

PageForge: A Near-Memory Content-Aware Page-Merging Architecture, MICRO 17  <br/>
                         
CSALT: context switch aware large TLB, MICRO 17  <br/>

ASLR on the Line: Practical Cache Attacks on the MMU, NDSS 17  <br/>

Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR, CCS 16  <br/>