The lecture started with DOS attack and ideas to mitigate the same at the DRAM level. Note that, the mitigations that we have discussed can mitigate side-channel and covert-channel also, uptocertain extent. 

 

Multiple solutions were proposed like aging based scheduling, round-robin sheduling and others at the DRAM controller that will isolate one core from other core. The conclusion was these policies will hamper performance big time and there is a need of some sort of spatial partitioning of DIMM resources (courtesy: Arun). We started with column, rows, (OS needs to be changed) and then decided bank might be a good resource to partition.

 

 

Final we came with spatio-temporal partitioning where the time window is partitioned for each core and the banks are partitioned too among the cores.

 

There was a discussion between MSHR entries and DRAM controller Q entries and how a back-pressure from LLC MSHR will go up to the core to inform the core that further loads and stores can not be sent to the LLC. Usually MSHRs are per core or per slice at the LLC. This issue was brough by Nabhiraj and answered by Riya and Arshalan.

 

The class is encouraged to find out the interval of one temporal window that will be allocated to one core and then spatial partitioning. Sujeet was in charge of framing this Q in Piazza but because of his busy schedule, he did not post it. Nabhiraj has posted the Q in the logistics tab. Thanks for that and no thanks to Sujeet.

 

PS: This idea is universal to many DRAM attacks.