Graphics Processing Units (GPUs) maintain a large register file to
increase the thread level parallelism (TLP), and hence the throughput.
However, register files dissipate a significant amount of power that
constitutes a major portion of the total leakage power. The leakage power
of a register file can be reduced by putting infrequently used registers
into low power (SLEEP or OFF) state after accessing them. However, to do
so, we need precise run-time register access information.

In this talk, I will present GREENER (GPU REgister file ENErgy Reducer): a
system to minimize leakage energy of the register file of GPUs. GREENER
employs a compile-time analysis to estimate the run-time register access
information. The result of the analysis is used to determine the power
state of the registers (ON, SLEEP, or OFF) after each instruction. We
propose a power optimized assembly instruction set that allows GREENER to
encode the power state of the registers in the executable itself. The
modified assembly, along with a run-time optimization to update the power
state of a register during execution, results in significant power
reduction.

We implemented GREENER in GPGPU-Sim simulator, and used GPUWattch
framework to measure the register file’s leakage power. Evaluation of
GREENER on 21 kernels from CUDASDK, GPGPU-SIM, Parboil, and Rodinia
benchmarks suites shows an average reduction of register leakage energy by
69.2% and maximum reduction of 88.41% with a negligible performance
overhead (0.05% slowdown on average).