The official syllabus for this course is available here.
For more details on the syllabus of the class, please see the topics in the Lecture Schedule below.
Laboratory Assignments - 40%
Laboratory Examination - 10%
Mid-Semester Examination - 20%
End-Semester Examination - 30%
Our department follows this anti-cheating policy strictly.
Lab Assignments
Lab groups and the lab schedule are Here
MIPS Programming Assignments
Verilog and FPGA Assignments
Lab Examination
In the week of April 17 to April 21 during the lab hours
Mid-Semester Examination
March 2, 2017 (Thursday) 8 am - 10 am at L18, L19 (all OROS)
Final Examination
April 27, 2017 (Thursday) 9 am - 12 am at L18, L19 (all OROS)
| Lecture | Date | Main Topic | Sub Topic | References |
| 1 | January 5, 2017 | Computer Abstractions and Technology | Course Overview, Introduction to Coputer Organization, Performance | [PH09 : 1.1 - 1.4] |
| 2 | January 6, 2017 | Performance (Contd.), The Power Wall, Uniprocessor to MultiProcessor, The SPEC Benchmark, Amdahl's Law | [PH09 : 1.5 - 1.8] | |
| 3 | January 11, 2017 | Computer Arithmetic | Signed and Unsigned numbers, Floating-Point Numbers | [PH09 : 2.4, 3.5 (up to page 238)] |
| 4 | January 12, 2017 | Instructions: Language of the Computer | Operations and Operands of the Computer Hardware | [PH09: 2.1 - 2.3] |
| 5 | January 13, 2017 | Logical Operations, Instructions for Making Decisions | [PH09: 2.6, 2.7] | |
| 6 | January 18, 2017 | Representing Instructions in the Computer, | [PH09: 2.5] | |
| 7 | January 19, 2017 | Supporting Procedures in Computer Hardware | [PH09: 2.8] | |
| 8 | January 20, 2017 | Communicating with People, 32-Bit Immediate and More Complex Addressing Modes | [PH09: 2.9, 2.10] | |
| 9 | January 21, 2017 | Tranlating and Starting a Program, Floating-Point Instructions | [PH09: 2.12, 3.5 (from page 247 to 254)] | |
| 10 | January 25, 2017 | Digital Logic Design | Gates, Truth Tables, and Logic Equations, Combinational Logic | [PH09 : C.1 - C.3], [MC07: 3.1 - 3.3, 4.8 - 4.10, 7.5 - 7.7] |
| 11 | January 27, 2017 | Hardware Description Language Verilog | [PH09 : C.4], [Chu08: Chapter 1, Chapter 3.1, 3.2] | |
| 12 | February 1, 2017 | Constructing a Basic Arithmetic Logic Unit | [PH09 : C.5] | |
| 13 | February 2, 2017 | Faster Addition: Carry Lookahead, Hardware Description Language Verilog (Contd.) | [PH09 : C.6], [Chu08: Chapter 3.3 -3.8] | |
| 14 | February 3, 2017 | Clocks, Memory Elements: Flip-Flops, Latches, and Registers, Timing Methodologies | [PH09 : C.7, C.8, C.11], [Chu08: Chapter 4.1, 4.2] | |
| 15 | February 8, 2017 | Memory Elements: SRAMs and DRAMs | [PH09 : C.9], [MC07: 7.2 - 7.4] | |
| 16 | February 9, 2017 | Finite-State Machines, Field Programmable Devices | [PH09 : C10, C.12], [Chu08: Chapter 5.1, 5.2] | |
| 17 | February 10, 2017 | Computer Arithmetic Algorithms and Hardware | Addition, Subtraction, Multiplication and Division | [PH09: 3.1 - 3.4] |
| 18 | February 15, 2017 | Floating-Point Addition and Multiplication, Associativity, Barrel Shifter | [PH09: 3.5,3.6], [Pil01: Chapter 2.2.1, 2.2.2] | |
| 19 | February 16, 2017 | The Processor | Building a Datapath | [PH09: 4.1 - 4.3] |
| 20 | February 17, 2017 | The Simple Datapath with the Control Unit | [PH09: 4.4] | |
| 21 | February 22, 2017 | A Multi-Cycle Implementation of Processor | [PH09-3: 5.5 (till page 329)] | |
| 22 | February 23, 2017 | The Control for Multi-Cycle Processor | [PH09-3: 5.5 (from page 330 to the end of the section)] | |
| | ||||
| 23 | March 8, 2017 | The Processor | An Overview of Pipelining | [PH09: 4.5] |
| 24 | March 9, 2017 | Pipelined Datapath and Control | [PH09: 4.6] | |
| 25 | March 10, 2017 | Data Hazard | [PH09: 4.7] | |
| | ||||
| 26 | March 22, 2017 | The Processor | Control Hazard, Exceptions | [PH09: 4.8, 4.9] |
| 27 | March 23, 2017 | Instruction Level Parallelism | [PH09: 4.10] | |
| 28 | March 29, 2017 | Memory Hierarchy | The Basic Structure of a Memory Hierarchy, The Basics of Caches | [PH09: 5.1, 5.2] |
| 29 | March 30, 2017 | Measuring and Improving Cache Performance | [PH09: 5.3] | |
| 30 | March 31, 2017 | Virtual Memory | [PH09: 5.4] | |
| 31 | April 5, 2017 | A Common Framework for Memory Hierarchies, Finite State Machine for Controlling a Simple Cache, Cache Coherence | [PH09: 5.5, 5.7, 5.8] | |
| 32 | April 6, 2017 | Storage and I/O Technologies | Dependability, Reliability and Availability, Disk and Flash Storage, Connecting Processors, Memory and I/O Devices, Interfacing I/O Devices to the Processor, Memory and Operating System | [PH09 : 6.1 - 6.6] |
| 33 | April 7, 2017 | Parallelism and I/O | [PH09 : 6.9] | |
| 34 | April 12, 2017 | Multicores, Multiprocessors, and clusters | Difficulty of Creating Parallel Processing Program, Shared Memory and Message Passing Multiprocessors | [PH09 : 7.1 - 7.4] |
| 35 | April 13, 2017 | | ||
[PH09] David A Patterson, John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 4th Edition, Morgan Kaufmann, 2009.
[PH09-3] David A Patterson, John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 3rd Edition, Morgan Kaufmann, 2009.
[MC07] M. Morris Mano, Michael D. Ciletti: Digital Design. 4th Edition, Pearson Education, 2008.
[Chu08] Pong P. Chu. FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version, John Wiley & Sons, Inc., 2008.
[Pil01] Matthew Rudolf Pillmeier. Barrel shifter design, optimization, and analysis. Lehigh University, 2001.