Workshop on Language, Compiler, and Architecture Support for GPGPU

Held in conjunction with HPCA/PPoPP 2010
Bangalore, 9th January 2010 (Morning)



Workshop program

9:00am to 10:00am Invited talk, Joy Chandra (Intel)
Title: GPGPU, The Road Ahead [PDF]
Abstract: I shall start by scanning the ecosystem of both past and present and highlight the common trends across graphics applications, APIs, and hardware toward increased programmability and complexity. The talk will then focus on the challenges faced in GPGPU across the entire spectrum of programmability, architectural efficiency, and the associated ecosystem in the area of benchmarks and debugging tools. I will then go over the Larrabee architecture highlighting the GPGPU aspects and the ecosystem that is being built to facilitate GPGPU. The talk will conclude by providing a glimpse of what future GPGPU space would be like and the challenges associated with it. Time permitting, a live demo of Larrabee will be shown.

10:00am to 10:25am PUG: A Symbolic Verifier of GPU Programs [PDF]
Guodong Li, Ganesh Gopalakrishnan, Robert M. Kirby (University of Utah), Dan Quinlan (LLNL)

10:25am to 10:45am Break

10:45am to 11:10am Modeling the CUDA Remoting Virtualization Behaviour in High Performance Networks [PDF]
Jose Duato, Antonio J. Pena, Federico Silla (UP Valencia), Rafael Mayo, Enrique S. Quintana-Orti (Universidad Jaume I)

11:10am to 11:35am Improving Accuracy through Selective Doubly Compensated Summation [PDF]
Matthew Badin, Lubomir Bic, Michael Dillencourt, Alexandru Nicolau (UC Irvine)

11:35am to Noon Data-layout Transformation for Structured-Grid Codes on GPU [PDF]
I-Jui Sung, Wen-mei Hwu (UIUC)

Noon to 12:25pm Effect of Instruction Fetch and Memory Scheduling on GPU Performance [PDF]
Nagesh B Lakshminarayana, Hyesoon Kim (Georgia Institute of Technology)

12:25pm to 12:50pm PLASMA: Portable Programming for SIMD Heterogeneous Accelerators [PDF]
Sreepathi Pai, Ramaswamy Govindarajan, Matthew Jacob Thazhuthaveetil (Indian Institute of Science)

Prolog

GPUs are evolving as massively threaded vector machines. While the primary design goal of the GPUs is efficient processing of the graphics stack, the massive parallelism available in these chips has lately opened up the possibility of carrying out general purpose computing on them. This computing paradigm is called GPGPU. Although manually mapping regular data parallel applications on GPUs has been explored quite extensively, making truly general purpose computing feasible on GPUs requires answering a number of important questions. This half-day workshop aims at bringing together the researchers and practitioners in this rapidly evolving area with a goal of addressing issues related to programming languages, programming models, compiler optimizations, and architecture to make GPGPU a conducive execution environment for regular as well as irregular applications. The topics of interest include, but are not limited to, the following.

  • New GPU architecture features to enhance GPGPU
  • Memory system innovations to enhance GPGPU
  • Implications of GPGPU on memory consistency models
  • Architecture support for single-chip CPU-GPU integration
  • Programming models and language support for GPGPU
  • Compiler optimization for GPGPU
  • Debugging/Performance visualization tools for GPGPU
  • Efficient synchronization support for GPGPU
  • Performance evaluation of irregular applications on GPUs
  • Energy-efficiency studies of GPGPU
  • GPGPU benchmarks


    • Call for papers

    The workshop invites submissions featuring unpublished results. The submissions must not exceed ten pages in two-column IEEE transaction style. The workshop will feature one invited keynote and a number of contributed papers selected from the submissions. All the papers and presentations will be made available online. However, publication in this workshop does not preclude later publication in regular conferences and journals.

    Submission instructions

    Please send your submission in PDF format to the following email address:
    gpgpu@cse.iitk.ac.in
    You will receive a confirmation email in response to your submission.

    Important dates

  • Submission deadline: October 20, 2009 (Extended to October 31, 2009 midnight PDT) [CLOSED]
  • Acceptance notification: November 24, 2009
  • Final paper deadline: December 5, 2009


    • Organizing committee

    Mainak Chaudhuri, IIT Kanpur
    Kalyan Muthukumar, Intel

    Program committee

    Rajesh Bordawekar, IBM
    Mainak Chaudhuri, IIT Kanpur
    Jonathan Cohen, nVIDIA
    Michael Garland, nVIDIA
    Milind Girkar, Intel
    Ajay Joshi, Intel
    David Kaeli, Northeastern University
    Subodh Kumar, IIT Delhi
    Dinesh Manocha, UNC Chapel Hill
    Andreas Moshovos, University of Toronto
    Kalyan Muthukumar, Intel
    P. J. Narayanan, IIIT Hyderabad
    Ben Sander, AMD
    Karu Sankaralingam, UW-Madison
    John Stone, UIUC
    Kumar Vemuri, Intel
    Peng Wu, IBM