Disassembler using High Level Processor Models

Nihal Chand Jain

under guidance of

Dr. Rajat Moona

  
 Introduction

Abstract

The design of a high performance system requires an integrated environment to simulate and analyze the performance of various design alternatives. In this thesis, we have developed a generic disassembler for an integrated environment where Sim-nML acts as the specification language for processor performance model. The Sim-nML, an extension of nML machine description formalism, is a simple, elegant and powerful language to model machine behavior at instruction level. As part of the thesis work, we have designed an intermediate representation (IR) for processor specification written in Sim-nML language. The IR is simple and facilitates the development of various tools such as assembler, compiler back-end generator, instruction set simulator, trace generator etc. based on the processor specification. A tool, IR-Generator, is developed which takes a processor specification written in Sim-nML language and produces it in the intermediate representation. Further, a Generic Symbolic Disassembler is developed which takes the intermediate representation of a processor and a relocatable binary file in ELF format as input and produces an equivalent program in assembly language of the processor. The disassembler is generic enough to be used for all type of processors.

Acknowledgments

I am grateful to my thesis supervisor, Dr. Rajat Moona, who guided me at every stage of this project with his valuable suggestions, whose qualities have attracted me a lot. His ideas have been of great help in exploring the areas which otherwise would have been impossible. I thank the Almighty for giving such a brotherly figure as my guide.

This work is done as a part of the ongoing research in Cadence Research Center at IIT Kanpur. I express my gratitude to Cadence India Ltd. for their enduring support to this work. Apart from the ample financial support provided by the fellowship, it has been a source of pAcknowledgments

I am grateful to my thesis supervisor, Dr. Rajat Moona, who guided me at every stage of this project with his valuable suggestions, whose qualities have attracted me a lot. His ideas have been of great help in exploring the areas which otherwise would have been impossible. I thank the Almighty for giving such a brotherly figure as my guide.

This work is done as a part of the ongoing research in Cadence Research Center at IIT Kanpur. I express my gratitude to Cadence India Ltd. for their enduring support to this work. Apart from the ample financial support provided by the fellowship, it has been a source of personal pride and motivation to be called a "Cadence Fellow".

I am also greatly indebted to Dr. Deepak Gupta and Dr. Sanjeev Agarwal for their guidance and support throughout my work. I express my heart-felt thanks to all the faculty members for teaching the principles in most exciting and enjoyable way.

I am greatly indebted to my seniors specially Atul and Kshitiz for helping me out in crucial situations. I would also like to thank V.Rajesh, Subhash and Shishir who has helped me with lots of ideas throughout the work. I thank all my MTech97 class-mates especially Professor (Zade), Bepari, Kapil, Atul, Manoj, Anna, Anjali, Uma, Prasad, Srikar, Gopi, Girish, Prasanna, Kousik and Major Ajay, for being affectionate and the source of inspiration for me. My gratitude goes to all of my MTech97 batch-mates, who made my stay in Hall-V, IITK a memorable one. I acknowledge the MTech98 batch for their exciting company. I wish I could express my thankfulness to all my old friends for their love, support and encouragement.

I thank my parents, my brothers, for their love and affection I have been receiving. I am grateful to all of them for their efforts in building my career. Finally, I would also like to thank God for being kind to me and driving me through this journey.
 

• Introduction
• Motivation
• Overview of Related Work
• Goals Achieved
• Organization of Report
• Intermediate Representation of Processor Models
• Sim-nML Language
• Sim-nML Grammar
• Design of an Intermediate Representation
• Simplification of Information by Substitution
• Simplifying the Hierarchy
• Representation of Attribute Definition
• Structure of the Intermediate Representation
• Conversion from High Level to Intermediate Representation
• Pass 1 : Macro Preprocessor
• Pass 2 : Parsing and Flattening the Hierarchy
• Design and Implementation of Disassembler
• Input Binary File (ELF) Structure
• Two Pass Design of Disassembler
• Resolving References
• Extracting Information from Intermediate Representation
• Extracting Syntax and Image of instructions
• Instruction Matching Algorithm
• Extracting Control Transfer Instruction
• Evaluation of Next Instruction Address
• Implementation Details of the Disassembler
• Initialization Phase
• First Pass of Disassembly
• Second Pass of Disassembly
• Disassembly of Other Sections
• Results and Conclusion
• Results
• Example 1 :
• Example 2
• Conclusion
• Future Work and Extensions
• Grammar of Sim-nML Language
• File Format of Intermediate Representation
• Meta Table
• Constant Table
• Resource Table
• Identifier Table
• Attribute Table
• Memory Table
• And-Rule Table
• Or-Rule Table
• Syntax Table
• Image Table
• String Table
• Integer Table
• Prefix-Attribute-Definition Table
• User's Manual
• IR-Generator
• Usage
• Disassembler
• Usage
• References
• About this document ...

  
 Introduction

Fri Jan 15 11:17:08 IST 1999