Abstract:

Designs are becoming more complex and time-to-market is shrinking given the demand for technological advances in the latest and greatest gadgets, consumer electronics, as well as industries such as automotive, high performance computing, etc.  This thirst for innovation translates to super-fast processors, memory components, interfaces, visual computing elements, etc. and NVIDIA is at the forefront of innovations in such designs. Needless to say, one of the main bottlenecks for quick time-to-market for such complex designs is verification closure. The talk will focus on how we have used formal verification as a means of not only verifying difficult problems effectively, but also shortening the verification time. The areas covered will include formal test-plan development, formal property verification, equivalence checking, clock gating verification, coverage closure, etc.


Speaker Bio:

Syed Suhaib is the CPU and Tegra SoC Formal Verification Team Lead and Manager at NVIDIA. He drives the formal verification effort across various projects for next-generation designs, starting from test plan development, to applications of various formal verification technologies. He is also involved with development of efficient methodologies and frameworks that are most effective for verification. Syed has a PhD in formal methods and modeling of communication protocols for intellectual property composition from Virginia Tech.